1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) and, more particularly, to a DRAM having a stress testing device for applying a voltage stress, e.g., when defect screening is performed in a wafer state (i.e., the DRAM which is not separated from a semiconductor wafer.).
2. Description of the Related Art
In a manufacturing process of semiconductor devices, in general, products are sorted into good ones and bad ones by a die-sorting test after a process for producing semiconductor wafers, and after the good ones are accommodated in packages, thereby obtaining their final form. The packaged products are screened. As a method of screening, burn-in is employed in many cases, in which electric-field acceleration and temperature acceleration can be simultaneously performed.
Published Unexamined Japanese Patent Application (Kokai) No. 3-35491 (T. Furuyama), which corresponds to U.S. patent application Ser. No. 544,614, discloses a semiconductor memory suitable for performing screening of memory chip regions on a semiconductor wafer, using a probe card and a prober before the die sort test. This screening can be performed efficiently in a short period of time.
In a commonly-used semiconductor memory, a noise killer MOS transistor is connected between one end of a word line and a ground node. The noise killer transistor prevents the voltage potential of a non-selective word line from entering a floating state during a precharge period or an active period in a normal operation mode, and prevents the level of a word line from exceeding the threshold voltage of a transfer gate of a memory cell because of noise or the like during either of these periods. This prevents data in memory cells from being destroyed.
If the noise killer transistor is in the ON-state when all word lines are selected and voltage stress is applied to the word lines to perform a screening, a through-current will flow from a voltage stress application power source to the ground node via the word line and noise killer transistor. Thus, it is desirable to provide a control means for controlling the noise killer transistor in order to apply the voltage stress to the word lines simultaneously when a voltage stress test is carried out on a DRAM.